DDV Project


The DDV project has been funded by Siemens Austria from 1994 to 1998. Currently, the VHDLDIAG tool is delivered to Siemens Austria for evaluation purposes. At this time VHDLDIAG and WFCOMP are not available for the public.
  • 1994 Start of the DDV project
  • 1995 First prototype implementation of VHDLDIAG and WFCOMP has been delivered to Siemens Austria. The functional dependency model was implemented. Diagnostic functionality restricted to the VHDL concurrent statements level.
  • 1996-98 Maintaining the VHDLDIAG and WFCOMP implementation. Extending VHDLDIAG. Adding an exact model for locating faults within VHDL processes.
  • Since 1998 VHDLDIAG implementation delivered and ready for evaluation (Siemens Austria). Theoretical work has been done for improving diagnosis. This includes the development of an exact model for VHDL concurrent and sequential statements (see publications).