IEEE ISMVL '96 Preliminary Program

ISMVL '96 Local Org. Comm. (elieee@usc.es)
Wed, 17 Apr 1996 19:53:03 +0200


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| 26th IEEE International Symposium on Multiple-valued Logic - ISMVL'96 |
| May, 29-31, 1996 |
| |
| and |
| |
| 1996 Workshop on Post-Binary Ultra-Large Scale of Integration - ULSI'96 |
| May, 28, 1996 |
| |
| Santiago de Compostela, Galicia, Spain |
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The Multiple-valued Logic Technical Committee of the IEEE Computer Society
will hold its 26th. annual symposium on May 29 - 31, 1996 in Santiago de
Compostela, Spain. The symposium will be sponsored by the University
of Santiago de Compostela, the Commission for the 5th. Centennial
Anniversary of the University of Santiago de Compostela and by the
IEEE Computer Society. The symposium will be co-sponsored by the General
Direction of Scientific and Technical Research (Spanish Ministry of
Education and Science), the honorable Council of Santiago de Compostela
and the Government of Galicia.

The University of Santiago de Compostela will host the Symposium on its South
campus, located in the new part of the city, very close to the old town. The
celebration of the 5th Centennial anniversary of USC frames the organization
of ISMVL '96.

ADVANCE PROGRAMME
=================

Tuesday, May 28, 1996
---------------------

09:00 ISMVL'96 On-site Registration

10:30 - 10:35 Opening Remarks: T. Sasao

10:35 - 11:35 SESSION ULSI 1 (Chair: D. M. Miller).
INVITED PRESENTATION : "Extensions of Decision
Diagrams to the Word-Level"

Rolf Drechsler
Albert-Ludwigs-University, Germany.

11:35 - 12:00 Coffee break

12:00 - 13:30 SESSION ULSI 2

13:30 - 15:00 Lunch

15:00 - 16:30 SESSION ULSI 3

16:30 - 16:45 Coffee Break

16:45 - 18:00 SESSION ULSI 4

18:00 Closing Remarks: T. Sasao

19:30 Guided visit to the Cathedral
20:30 Reception at the Council of
Santiago de Compostela

Wednesday, May 29, 1996
-----------------------

08:30 - 09:30 ISMVL'96 On-site Registration

09:30 - 09:45 Opening Remarks

09:45 - 10:45 INVITED ADDRESS: "As you like them:
Connectives in Fuzzy Logic"

Keynote Speaker:
Prof. Dr. Claudi Alsina
Open University of Catalunya, Spain

11:00 - 11:30 Coffee Break

11:30 - 12:45 PARALLEL SESSIONS 1A AND 1B

13:00 Lunch
Meeting of the Executive Committee

15:00 - 16:40 PARALLEL SESSIONS 2A AND 2B

16:40 - 17:10 Coffee Break

17:10 - 18:40 PARALLEL SESSIONS 3A AND 3B

Thursday, May 30, 1996
----------------------

09:00 - 10:45 SPECIAL SESSION: "Helena Rasiowa. In memoriam"
Invited Speakers:
Prof. Dr. G. Malinowski
(Lodz University, Poland)
"Helena Rasiowa - a view of the academic
trajectory and the influence upon Polish
and international scientific community"

Prof. Dr. J.M. Font
(University of Barcelona, Spain)
"On the contributions of Helena Rasiowa
to Mathematical Logic"

Prof. Dr. T. Sales
(Polytechnical Univ. Of Catalunya, Spain)
"From pure to approximate logic"

11:00 - 11:30 Coffee Break

11:30 - 12:45 PARALLEL SESSIONS 4A AND 4B

13:00 Lunch
Meeting of the Symposium Committee

15:00 Tentative excursion

Friday, May 31, 1996
--------------------

09:45 - 10:45 INVITED ADDRESS: "Inference in Fuzzy Logic
via Generalized Constraint Propagation"

Keynote Speaker:
Prof. Dr. Dr. h.c. Lotfi A. Zadeh
University of California, Berkeley, U.S.A.

10:45 - 11:15 Coffee Break

11:15 - 12:05 PARALLEL SESSIONS 5A AND 5B

12:10 - 12:55 Plenary Session

13:00 Lunch

15:00 - 16:40 PARALLEL SESSIONS 6A AND 6B

16:40 - 17:10 Coffee Break

20:00 Symposium Banquet
===================================================================

Tuesday, May 28 ULSI '96 Oral Presentations
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All sessions of ULSI will be held at the "Aula Magna" Room of the
Faculty of Physics (2nd floor).

SESSION ULSI 2 : Decision Diagrams I (Chair: C. Moraga)

12:00 Complex Spectral Decision Diagrams
Bogdan J. Falkowski
(Nanyang Technological University, Singapore).
12:30 Fourier Decision Diagrams for Optimization of Discrete Function
Representations
Radomir Stankovic
(Brace Taskovica, Yugoslavia)
13:00 On Using Decision Diagrams to compute Logic and Arithmetic
Polynomial Forms for Incompletely Specified MVL Functions
V.Shmerko, S.Yanushkevich
(Institute of Computer Science, Szczecin, Poland)

SESSION ULSI 3: Decision Diagrams II (Chair T. Sasao)

15:00 Exact Minimization of Networks with Complex Gates using Terminal
Suppressed Binary Decision Diagrams and Dissected Pairs
Marek Perkowski,
(Portland State University, U.S.A.)
15:30 Using Decision Diagrams to Design ULMs for FPGAs
Zeljko Zilic
(University of Toronto, Canada)

16:00 A Note on Symbolic Simulation using Decision Diagrams
Rolf Drechsler, Andreas Hett, Bernd Becker,
(Albert-Ludwigs-University, Germany)

SESSION ULSI 4: Architectural and Nano-electronics Strategies for 2D and 3D
ULSI Signal Processing
Organizer: Lutz J. Micheel

17:10 Panelists:
Gary Frazier, (Corporate R&D, Texas Instruments, Dallas, U.S.A.)
Takahiro Hanyu, (Tohoku University, Sendai, Japan)
Hans Hartnagel (Institute of Technology, Darmstadt, Germany)
Gernot Pomrenke (Advanced Research Projects Agency, Arlington, U.S.A.)
Takao Waho, (NTT LSI Laboratories, Atsugi, Japan)

Wednesday, May 29 ISMVL '96 Oral Presentations
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SESSION 1A: Switching Theory

11:30 Verification of Multi-valued Logic
Networks.
Rolf Drechsler.
(University of Freiburg, Germany)
11:55 New Interpolation Algorithms for Multiple-
Valued Reed-Muller Forms.
Zeljko Zilic, Zvonko G. Vranesic
(University of Toronto, Canada)
12:20 Family of fast mixed arithmetic logic
transforms for multiple-valued input binary
functions.
Susanto Rahardja, Bogdan J. Falkowski
(Nanyang Technological University,
Singapore)

SESSION 1B: Devices

11:30 A literal gate using resonant-tunneling devices
T. Waho, K. J. Chen, M. Yamamoto
(NTT LSI Laboratories, Japan)
11:55 A Multiple-Valued Ferroelectric Content-
Addressable Memory
Ali Sheikholeslami, P. Glenn Gulak
(University of Toronto, Canada)
Takahiro Hanyu
(Tohoku University, Japan)
12:20 Interband RTDs with Nanoelectronic HBT-
LED Structures for Multiple-Valued
Computation
Lutz J. Micheel
(Wright Laboratory, U.S. Air Force, USA)
Hans L. Hartnagel
(University of Darmstadt, Germany)

SESSION 2A: Fault Modelling, Fault Diagnosis

15:00 Fault Diagnosis System based on Sensitivity
Analysis and Fuzzy Logic
Luis J. de Miguel, Margarita Mediavilla,
Jose R. Peran
(University of Valladolid, Spain)
15:25 Fault Models for the Multi-valued Current
Mode Circuit
Yeong-Jar Chang, Chung Len Lee
(National Chiao Tung University, Taiwan)
Jwu E Chen, Chung-Hwa
(Polytechnic Institute, Taiwan)
15:50 Testability of Generalized Reed-Muller
Circuits
Elena V. Dubrova, Jon C. Muzio
(University of Victoria, Canada)
16:15 Design of One-Vector Testable Binary
Systems Based on Ternary Logic
Mou Hu
(Shanghai Tiedao University, China)

SESSION 2B: LOGIC 1

15:00 Commodious Axiomatization of Quantifiers in
Multiple-valued Logic
Reiner Haehnle
(University of Karlsruhe, Germany)
15:25 The Incidence Propagation Method
Weiru Liu
(University of Ulster at Jordanstown, Ireland)
15:50 Approximative Conjunctions Processing by the
Multiple-valued Logic
Herman Akdag, Myriam Mokhtari
(University of Paris, France)
16:15 Intuistionistic Counterparts of Finite-Valued
Logics
Matthias Baaz
(University of Vienna, Austria)
Christian Fermuller
(Stanford University, USA)

SESSION 3A: Circuits, Logic Design I

17:10 A ternary systolic product-sum circuit for
GF(3^m) using neuron MOSFETs
Noriaki Muranaka
(Kansai University, Japan)
Shigenobu Arai
(Nintendo Co., Ltd., Japan)
Shigeru Imanishi
(Kansai University, Japan)
D. Michael Miller
(University of Victoria, Canada)
17:35 New MVL-PLA Structures based on
Current-mode CMOS Technology
Mostafa Abd-El-Barr, M. Nayyar Hasan
(King Fahd University of Petroleum and
Mnerals, Saudi Arabia)
18:00 Design of highly parallel linear digital
circuits based on a symbol-level
redundancy
Masami Nakajima, Michitaka Kameyama
(Tohoku University, Japan)

SESSION 3B: Logic II

17:10 Non-Archimedean Models of Lukasiewicz Logic
Antonio Di Nola
(University of Naples, Italy)
17:35 A Necessary and sufficient condition for
Lukasiewicz logic functions
Noboru Takagi, Kyoichi Nakashima
(Toyama Prefectural University, Japan)
Masao Mukaidono
(Meiji University, Japan)
18:00 Propositional skew Boolean logic
R. J. Bignall, M. Spinks
(Monash University, Australia)

Thursday, May 30 ISMVL '96 Oral Presentations
-------------------------------------------------------------------------

SESSION 4A: Algebra I

11:30 Associativeness versus Recursiveness
V. Cutello
(University of Catania, Italy)
E. Molina, J. Montero
(Complutense University of Madrid, Spain)
11:55 Rational Transitivity and its Models
Hassan Bezzazi, Ramon Pino Perez
(University of Lille, France)
12:20 Several Remarks on the Complexity of Set-
Valued Switching Functions
Dan A. Simovici
(University of Massachusetts at Boston, USA)
Corina Reischer
(University of Quebec a Trois-Rivieres, Canada)

SESSION 4B: Artificial Intelligence, Reasoning.

11:30 Petri Net Representation of Fuzzy Reasoning
under Incomplete Information
A. Bugarin, P. Carinena, M. Fdez-Delgado,
S. Barro
(University of Santiago de Compostela, Spain)
11:55 Weight Structures for Approximate
Reasoning with Weighted Expressions
Stephan Lehmke
(University of Dortmund, Germany)
12:20 Reasoning in inconsistent stratified
knowledge bases
Salem Benferhat, Didier Dubois, Henri Prade
(University Paul Sabatier, France)

Friday, May 31 ISMVL '96 Oral Presentations
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SESSION 5A: Algebra II

11:15 On Isomorphisms between the Lattice of
Tolerance Relations and Lattices of
Clusterings
Helmut Thiele
(University of Dortmund, Germany)
11:40 An Algebraic Approach to Hyperalgebras
Ivo G. Rosenberg
(University of Montreal, Canada)

SESSION 5B: Soft Computing

11:15 Wave-parallel computing technique for neural
networks based on amplitude-modulated waves
Yasushi Yuminaka, Yoshisato Sasaki
(Gunma University, Japan)
Takafumi Aoki, Tatsuo Higuchi
(Tohoku University, Japan)
11:40 Design of multivalued circuits using genetic
algorithms
Wenjun Wang, Claudio Moraga
(University of Dortmund, Germany)

SESSION 6A: Circuits, Logic Design II

15:00 Quaternary Universal-Literal CAM for
Cellular Logic
Takahiro Hanyu, Manabu Arakaki,
Michitaka Kameyama
(Tohoku University, Japan)
15:25 Multi-Valued Decoder Based on Resonant
Tunneling Diodes in Current Tapping Mode
Hao Tang and H. C. Lin
(University of Maryland, USA)
15:50 Low-Energy Logic Circuit Techniques for
Multiple-Valued Logic
K. Wayne Current, Vojin G. Oklobdzija.,
D. Maksimovic
(University of California at Davis, USA)
16:15 On the Use of VHDL as a Multi-Valued
Logic Simulator
Come Rozon
(Royal Military College of Canada)

SESSION 6B: Decision Diagrams

15:00 Planarity in ROMDD's of Multiple-Valued
Symmetric Functions
Jon T. Butler, Jeffrey L. Nowlin
(Naval Postgraduate School, USA)
Tsutomu Sasao
(Kyushu Institute of Technology, Japan)
15:25 Multiple-valued Decision Diagrams with
Symmetric Variable Nodes
D.M. Miller
(University of Victoria, Canada)
N. Muranaka
(Kansai University, Japan)
15:50 A Method to Represent Multiple-Output
Switching Functions by using Multi-Valued
Decision Diagrams
Tsutomu Sasao
(Kyushu Institute of Technology, Japan)
Jon Butler
(Postgraduate Naval School, USA)
16:15 Complex spectral decision diagrams
Bogdan J. Falkowski, Susanto Rahardja
(Nanyang Technological University,
Singapore)

SESSION 7A: Algebra III

17:10 Polynomial Completeness Criteria in Finite
Boolean Algebras
Boris A. Romov
(New York, USA)
17:35 Efficiently irreducible bases in multiple-
valued logic
Grant Pogosyan
(International Christian University, Japan)
18:00 On the Lattice of Partial Clones on a Finite Set
Lucien Haddad, Jean Fugere (Royal
Military College of Canada)
18:25 The Deepest Repetition Free
Decompositions of non-singular functions
of finite-valued logics are almost
coinciding
Fedir Sokhatsky
(Pedagogical Institute of Vinnytsia, Ukrainia)

SESSION 7B:LOGIC III

17:10 DT - An Automated Theorem Prover for
Multiple-Valued First-Order Predicate Logics
Stefan Gerberding
(University of Darmstadt, Germany)
17:35 Logic expressions of monotonic multiple-
valued functions
Kyoichi Nakashima, Yutaka Nakamura, Noboru
Takagi (Toyama Prefectural University, Japan)
18:00 Techniques of Computing Logic Derivatives
for MVL-Functions
Vladimir Shmerko, S. Yanushkevich
(Technical University of Szczecin, Poland)
V. Levashenko, I. Bondar
(Belarussian State Economic University,
Republic of Belarus)
18:25 The Logical not-Polynomial Forms to
represent Multiple-valued Functions
Elena Zaitseva, Tatyana Kalganova
(Belarussian State Economic University,
Reublic of Belarus)
Evgeny Kochergov
(Institute on Problems of Criminology,
Criminalistics and Forensic Expertise,
Republic of Belarus)

SYMPOSIUM REGISTRATION
----------------------
The Registration Desk of ISMVL '96 will be placed at the Faculty of Physics,
South Campus of the University of Santiago de Compostela. Symposium
sessions will be held at the Faculty of Physics and Faculty of Philosophy, while
Keynote lectures will be delivered at the University Auditorium, also placed
at the South Campus.

ISMVL'96 registration includes admission to the symposium technical sessions,
the opening reception and visit, refreshment breaks, conference dinner and a
copy of the Symposium's proceedings. Authors are reminded that at least one
author should attend the Symposium to present accepted papers.

The Conference Sites are placed in the University South Campus, located in
walking distance (10-20 minutes) from a number of restaurants both in the old
and the new part of the city. During the Conference, lunch meals will be
offered at a University Self-Service Restaurant placed very closely to the
Conference Sites. Tickets for these meals must be purchased at registration
time.

The Conference dinner will be offered on Friday, May 31. Additional tickets
for accompanying persons can be purchased during the Conference.

PAYMENT
-------
IEEE Member Non-Member Student (wo/proceedings)

Early $250 US (...) $315 US (...) $30 US (...)
By May 1 30000 Ptas 37800 Ptas 3600 Ptas

Late/On-Site $300 US (...) $375 US (...) $50 US (...)
After May 1 36000 Ptas 45000 Ptas 6000 Ptas


Please make checks out to:

ISMVL 96

or bank transfers out to:
ISMVL 96
Bank: BANCO BILBAO VIZCAYA
Agency: C/Alfredo Branas. Santiago de Compostela
Account no.: 0182-0624-32-001-150268-7

Return by mail the filled-in form attached at the end of the message with payment to:

NOVA DE CONGRESOS
Address:
R/ Xeneral Pardi~nas, 32-1
E-15701 Santiago de Compostela
Spain
Fax: + 34 81 561199
Phone: +34 81 574348

ARRIVALS
--------
Santiago de Compostela is served by an International Airport,
located at a 12 km. distance from the city downtown. Flights to Santiago
from Madrid (10 flights a day, 60 min. of travel), Barcelona (4 flights a day,
75 min. of travel) and some other spanish and european cities provide
connections for international attendees arriving from outside Spain. Santiago
can also be reached by train or bus from most Spanish towns and a number of
European cities. Bus and taxi services connect the Airport with downtown
Santiago, where hotels and conference sites are placed.

HOTELS INFORMATION
------------------
Reservations have been made in some hotels both in the old town and in
the new part of the City. All questions concerning hotel reservations
should be made through the Conference Agency NOVA DE CONGRESOS.
The number of rooms is limited and will be available on a first-come
first-served basis. Though hotels are located at walking distance of the
Conference Site or the old town monuments, organization will provide a bus
service connecting all hotels and the Conference Site. Information map about
hotels location, hotels reservation form and prices is available at the
Conference WWW

http://elgsi.usc.es/ISMVL-96

and anonymous ftp servers

elgsi.usc.es/ISMVL-96

-----REGISTRATION FORM: PLEASE CUT AND RETURN TO "NOVA DE CONGRESOS" ----

26th IEEE International Symposium
on Multiple-valued Logic ISMVL '96

29-31 May, 1996
Santiago de Compostela, Galicia, Spain.
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SYMPOSIUM REGISTRATION FORM
===========================


NAME: (Last)_______________________________________________________

(First)______________________________________________________

IEEE MEMBER NUMBER:________________________________________________

AFFILIATION:_______________________________________________________

ADDRESS:___________________________________________________________

___________________________________________________________

CITY:________________________________________

STATE/PROVINCE:____________________________________________________

COUNTRY:_______________________ ZIP CODE:________

DAYTIME TELEPHONE: (+___)_____________________

FAX: (+___)_____________________

EMAIL ADDRESS:_____________________________________________


PLEASE RSVP FOR POST-BINARY ULSI WORKSHOP (May, 28, 1996)
(no charge for attendance)

No, I cannot attend. (...)

Yes, I will attend. (...)

MEALS
=====

Please RSVP for lunch meals during the following Conference days:

__ May 28 __ May 29 __ May 30 __ May 31

Total meals: ___ @7$/800 Ptas. each= __________

TOTAL PAYMENT ENCLOSED:________________ $/Ptas.

--------------------END OF REGISTRATION FORM-------------------------